1. Field of the Invention
The present invention relates to testing of integrated circuits, and more specifically to a method and apparatus to improve edge placement accuracy of signals generated by test equipment.
2. Related Art
Test equipment is often used to test integrated circuits/devices after fabrication. In a typical scenario, a test equipment generates various signals required for testing an integrated circuit (IC), and examines the generated output to determine whether a tested IC/device (“device under test”, DUT) operates in a desired manner or not.
Page of One general requirement with test equipment is that the signals be generated with appropriate timing. That is, the edges of the signals (which generally drive the transitions from one state to another) need to occur with a desired gap/duration, and with a desired relative positions with respect to other signals. For example, when a clock signal is used to sample data, the transitions of the data and clock signals need to satisfy the setup and hold time considerations, well known in the relevant arts.
However, the signals used for testing may not be generated accurately due to reasons such as the inherent nature of hardware components of test equipment. The degree of deviation may not be the same for all the generated signals. Accordingly, many commercially available test equipment specify the degree of deviation from accurate delays with which the test signals may be generated. For example, Catalyst test equipment (CAT50 and CAT400 products with a DRATE between 50–400 MHz) commercially available from Teradyne, Inc., (321 Harrison Avenue, Boston, Mass. 02118—2238 USA, Phone Number: +1/617 482—2700) specifies that the deviation can be between +/−282 ps (pico-seconds) to +/−700 ps.
One problem with such different degree of deviations is that timing requirements of the signals to test ICs may not be met. For example, to test integrated circuits operating at a frequency of 840 MHz, equals a time period of about 1190 ps. Achieving both setup and hold times within the 1190 ps with such high degree of deviation within +/—50 ps (pico_seconds) may present challenges.
What is needed at least for such reasons is a method and apparatus to improve edge placement accuracy of signals generated by test equipments.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.